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I am trying to use P17 & P18 for SCL! & SDA1 respectiely on the PRO. Since I have been having a problem using the I2C bus, I started digging into the documentation for the 2103.

I ran across a bit of conflicting information. For P17 UM10161 states:

SCL1 — I2C1 clock Input/output. Not open-drain.

For P18 UM10161 states:

SDA1 — I2C1 data Input/output. Not open-drain.

I have these pins pulled up to 5.0 Volts through 2.2K Ohm resistors. Since these pins are not Open Drain, my High levels may not reach the 0.7 VDD spec of the receiving part.

You probably need to level shift the I2C lines.
I use a couple of 2N7000 FETs and the schematic on page 10 of NXP application note AN97055
"Bi-directional level shifter for I²C-bus and other systems"

http://ics.nxp.com/support/documents/in ... n97055.pdf

The inputs are not true open drain, but when properly configured for i2c use, they will only actively pull down, and the external user supplied pullups will bring levels to whatever the supply is. If that's 5V the high level will be within a few millivolts of 5V. You should not need any level shifters (the IOs are 5V tolerant)

The data sheet highlights the non open drain nature ONLY if you intend to use the part in a system where the i2c devices can be run from separate power supplies AND the section including the LPC2103 is powered down. This is because ALL push-pull type CMOS outputs have parasitic diodes to the supply rails. What that means is that if the device is powered the input/output will look like a load that is a diode to the power supply which will look like a relatively low impedance to GND.